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Lattice Semiconductor
CSIX-to-PI40 IP Core User’s Guide
Parameter Descriptions
The list of parameters used for con?guring the CSIX-to-PI40 core is listed below. The values of these parameters
are to be set and must be done prior to synthesis or functional veri?cation.
Table 1. User Con?gurable Parameters
No.
1
2
Parameter
NUM_OF_CHANNELS
PI40_CELL_SIZE
Description
Number of CSIX channels
PI40 cell size and corresponding Cframe
Choice
1 or 2
76, 84 or 92 bytes
Default
1
92 bytes
MAX_FRAME_PAYLOAD_SIZE (56,64,72).
3
4
PROTECTION
BUFFER_TYPE
Support ability to switch between two fabrics.
Buffer type used for external CSIX Pins.
Yes or no
LVCMOS or HSTL
yes
LVCMOS
Signal Descriptions
Table 2. Signal De?nitions of CSIX-to-PI40 Core
Signal Name 1
Direction
Width (Bits)
Description
CSIX Interface (FPGA Primary I/Os)
c6_data_in_N_ext[31:0]
c6_parity_in_N_ext
c6_sof_in_N_ext
c6_clk_in_N_ext
c6_data_out_N_ext[31:0]
c6_parity_out_N_ext
c6_sof_out_N_ext
c6_clk_out_N_ext
Input
Input
Input
Input
Output
Output
Output
Output
32
1
1
1
32
1
1
1
Inbound Data
Inbound Parity (Odd)
Inbound Start of Frame
Inbound Clock (100MHz)
Outbound Data
Outbound Parity (Odd)
Outbound Start of Frame
Outbound Clock (100MHz)
SERDES Interface (FPGA Primary I/Os)
hdinna[a:d]
hdinpa[a:d]
hdoutna[a:d]
hdoutpa[a:d]
hdinnb[a:d]
hdinpb[a:d]
hdoutnb[a:d]
hdoutpb[a:d]
Input
Input
Output
Output
Input
Input
Output
Output
1
1
1
1
1
1
1
1
SERDES receive data input
SERDES receive data input
SERDES receive data output
SERDES receive data output
SERDES receive data input
SERDES receive data input
SERDES receive data output
SERDES receive data output
Register Interface (FPGA Primary I/Os, Do Not Replicate)
mpi_clk
mpi_addr[14:31]
mpi_rdwr_n
mpi_strbn
mpi_tsz[0:1]
mpi_burst
mpi_bdip
cs0n
cs1
mpi_ta
mpi_retry
mpi_tea
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
1
18
1
1
2
1
1
1
1
1
1
1
Clock (50 MHz)
Address bits
Write High / Read Low
Data transfer strobe
Data transfer size
Active low burst transfer indicator
Active low for processor request of second beat
Active low chip select
Active high chip select
Active low acknowledge to processor
Active low retry request to processor
Active low indicator to processor of internal bus error
4
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